| Paper: | DISPS-P1.6 |
| Session: | Implementation of Signal Processing Systems II |
| Session Time: | Thursday, April 23, 16:00 - 18:00 |
| Presentation Time: | Thursday, April 23, 16:00 - 18:00 |
| Presentation: |
Poster
|
| Topic: |
Design and Implementation of Signal Processing Systems: Algorithm and architecture co-optimization |
| Paper Title: |
A COST-ERROR OPTIMIZED ARCHITECTURE FOR 9/7 LIFTING BASED DISCRETE WAVELET TRANSFORM WITH BALANCED PIPELINE STAGES |
| Authors: |
Alireza Aminlou; University of Tehran | | |
| | Fatemeh Refan; University of Tehran | | |
| | Mahmoud Reza Hashemi; University of Tehran | | |
| | Omid Fatemi; University of Tehran | | |
| | Saeed Safari; University of Tehran | | |